 | STC-2026: SemiconTantra Conference 2026 PUNE, India, August 22, 2026 |
| Conference website | https://www.semicon-tantra.org/events/stc-2026 |
| Submission link | https://easychair.org/conferences/?conf=stc2026 |
| Abstract registration deadline | May 17, 2026 |
| Submission deadline | May 17, 2026 |
| Notification of Acceptance | June 30, 2026 |
| Camera-ready Paper Submission | July 31, 2026 |
| Conference Date | August 22, 2026 |
SemiconTantra Conference – 2026 is Technical Conference in the Semiconductor Domain intended to bring in Academia and Research community, Industry Professionals and Startups on one platform to discuss, deliberate and showcase advancements and trends in Semiconductor Design for AI Enabled Systems. Students, Industry Professionals, Startups from both Chip Design and System Design companies are expected to benefit from this conference and apply these learnings to design and Develop next generation products for AI enabled Systems.
Submission Guidelines
All papers must be original and not simultaneously submitted to another journal or conference. The following paper categories are welcome:
- Full papers
- Posters
Theme
Semiconductor Design and Hardware Platforms for AI-Enabled Intelligent Systems
Submission Links
Paper Submission Link : Paper Submission Link
Download Tempates : Download Template
Paper Submission Tracks
Note : Papers can be submitted to the any tracks listed below, but not limited to these areas. Submissions in related domains are encouraged.
Track 1: Advanced Circuit Design for AI Hardware
Scope
- Analog, digital, and mixed-signal circuits for AI workloads
- High-speed, low-power, and energy-efficient circuit techniques
- Memory circuits (SRAM, DDR/HBM, NVM) for AI accelerators
- Clocking, power management, and signal integrity
- Reliability, variability, and testability at advanced nodes
Track 2: Semiconductor Devices and Technology Innovations
Scope
- Advanced CMOS and post-CMOS devices
- Emerging devices (FinFET, GAAFET, TFET, CNTFET, memristors)
- Device modelling and characterization for AI applications
- 3D integration, heterogeneous integration, and packaging
- Co-Packaged Optics
Track 3: IP Design, Verification, and Reuse for AI Systems
Scope
- Processor, accelerator, memory, and interface IPs
- IP verification, validation, and security
- Reusable and configurable IP frameworks
- Licensing, standardization, and interoperability challenges.
Track 4: SoC and System Architecture for AI-Enabled Computing
Scope
- SoC architectures for edge, cloud, and embedded AI
- Heterogeneous computing (CPU–GPU–NPU integration)
- High Performance SoC Fabric and Memory Subsystems
- HW–SW co-design and system-level optimization
- Performance, power, and area (PPA) trade-offs
Track 5: Hardware Platforms and Reference Architectures
Scope
- AI hardware platforms and development boards
- FPGA- and ASIC-based AI platforms
- Platform-level optimization and benchmarking
- Deployment frameworks for edge and embedded AI
- Case studies and real-world system implementations
Track 6: Design Automation and EDA using AI
- EDA tools for circuit, IP, and SoC design
- Efficiency and Productivity Boost with AI-assisted Chip Design
Track 7: Hardware Security, Safety, and Reliability in AI first world
- Hardware Security, trusted IP, and secure SoCs
- Safety-critical AI systems (automotive, medical, industrial)
Committees
Technical Program Committee
- Dr. Prashant Bartakke, Associate Professor, CoEP Technological University, Pune
- Dr. Ganesh C Patil, Associate Professor, VNIT Nagpur
- Mr. Vinay Somanache, Distinguished Engineer, Cadence Design Systems, Pune
- Mr. Mrugesh Walimbe, Founder Mrug Sutantra, Pune [Ex Intel, Ex Marvell]
Publication Chair
- Dr Mansi Subhedar - HoD, Electronics and Computer Science Department, PHCET, Mumbai
Organizing committee
- General Chair - Apoorwa Kapse, Founder and Director - SemiconTantra
- Organizing Chair - Guari Deval, Founder QubeHR
- Sponsorsihp Chair - Gaurav Bhojane, Director, Cadence Design Sytems
Contact
All questions about submissions should be emailed to : tpc-stc-2026@semicon-tantra.org